Reciever comprising a digitally controlled capacitor bank

ABSTRACT

Receiver comprising an RF input filter including a digitally controlled capacitor bank with n capacitors being controlled by a tuning control signal for varying the tuning frequency of the RF input filter within a tuning range. For an improvement of the receiver in price/performance ratio the n capacitors of the digitally controlled capacitor bank are monolythically integrated, whereas the bandwidth of the tunable RF input filter is being adjusted to the maximum relative spread of said capacitors. A continuous tuning control signal is being supplied through an analogue to digital (AD) converter to said capacitor bank and to a first input of a differential stage, an output of the AD converter being coupled through a digital to analogue (DA) converter to a second input of a differential stage, an output of the differential stage being coupled to a control terminal of a variable capacitance diode being arranged in parallel to the digitally controlled capacitor bank.

[0001] The invention relates to a receiver comprising a tuning circuitincluding a digitally controlled capacitor bank with n capacitors beingmonolithically integrated in planary form and being controlled by atuning control signal, as well as to a capacitor bank. A receiver usinga digitally controlled capacitor bank of this type is known e.g. fromU.S. Pat. No. 4,216,451.

[0002] The capacitor bank of the known receiver provides a variablecapacitance, included in a filter circuit and is controlled toincrementally vary the tuning frequency of the filter and/or thereceiver. The use of a capacitor bank instead of a single variablecapacitance diode, allows to lower the bias voltage and to avoid theneed for DC/DC converters. Furthermore, the n capacitors of thedigitally controlled capacitor bank being monolithically integrated inplanary form enable to optimise the above receiver and/or the capacitorbank used therein, in terms of price/performance ratio and in particularin tuning behaviour.

[0003] However, In practice, the component values of circuit elementsimplemented in planary technology and in particular in integratedcircuit (IC) technology have absolute and relative spread. Absolutespread is understood to be the spread in the actual component valuesfrom a wanted or average value, whereas relative spread is understood tobe the spread in the component values of the elements relative to eachother. Absolute spread is mainly caused by variation of the thickness orthe composition of planar layers, whereas relative spread is caused bythe inhomogenities along the X and Y axes of the planar layers. Bothtypes of spread cause the actual value of integrated elements to deviateunpredictably from a target value, which in particular for relativelysmall values of the capacitance may amount to 30% or more. This hasprevented so far to integrate the capacitor bank for use in a receivertuning circuit. The invention, however, is based on the recognition thatin the above integrated capacitor bank, said spread can be preventedfrom affecting the accuracy of the capacitance value of the capacitorbank and/or the tuning frequency.

[0004] In consequence, amongst other things, it is an object of theinvention is to minimise the overall spread of the capacitance value ofthe capacitor bank.

[0005] Now therefore, according to one of its aspects, the invention ischaracterised by said n capacitors providing various capacitance valuesincluding a unity capacitor covering a unity IC surface, whereincapacitors having capacitance values smaller than said unity capacitorcover respective IC surfaces, which in proportion to their value aresmaller than said unity IC surface and wherein capacitors havingcapacitance values greater than said unity capacitor are being formed byclusters of capacitors, each covering an IC surface corresponding tosaid unity IC surface.

[0006] This measure is based on the recognition that the relative spreadof an integrated element, and in particular an integrated capacitorincreases with a decreasing IC surface thereof, whereas identicalelement structures decreases in relative spread with the square root ofthe multiplicity of application thereof. Said measure therewith allowsby a proper choice of the unity capacitor to minimise the total spreadin the capacitance value of the capacitor bank.

[0007] In a preferred embodiment of the invention said n capacitors forma binary weighted sequence of capacitance values ranging from 2⁰ to2^(n−1), whereas said unity capacitor is chosen to correspond to acapacitance value 2 ^(k), k being larger than 1 and smaller than n.

[0008] In a further preferred embodiment of the invention n is in theorder of magnitude of 10, whereas k is being chosen in a range between 3and 8. By applying this measure optimal use is made of the IC surfacedependent spread of the capacitors to obtain a minimum overall spread ofthe capacitance of the capacitor bank at each value within the tuningrange.

[0009] Preferably said unity capacitor being chosen to define the upperboundary limit of the tuning range in compensation parasitic effects.

[0010] Furthermore the above composition of capacitors in clusters ofunity capacitors introduces a degree of freedom in the lay out design tofurther minimise the overall spread in the individual integratedcapacitors of the capacitor bank.

[0011] Another preferred embodiment of the invention is thereforecharacterised in that said clusters of unity capacitors are beingsurrounded by isolated dummy capacitors. This measure allows tocompensate for spread in the capacitance values of the capacitors due toproximity effects.

[0012] To reduce parasitic effects, such receiver is preferably beingcharacterised in that the capacitors of the capacitor bank arestructured in lay out to form clusters having minimum parasitic wiringeffects.

[0013] Another object of the invention is to improve and simplify thecontrol of the capacitor bank.

[0014] Therefore, a receiver and/or capacitor bank comprising ncapacitors being controlled by a (tuning) control signal, according tothe invention is characterised by an AD converter for converting ananalogue tuning control signal into an m bit binary signal being coupledto a bitnumber conversion device for converting said m bit binary signalinto an n bit binary signal, m being smaller than n, said n bit binarysignal including bits 1 to N respectively controlling capacitors 1 to nof the capacitor bank.

[0015] This measure is based on the recognition that the number ofbinary weighted capacitor values necessary to obtain an appropriatedegree of accuracy in tuning frequencies is smaller than n, being thenumber of binary weighted capacitors of the capacitor bank needed tocover the tuning range. This measure allows to use an analogue tuningcontrol signal for tuning the RF input filter and furthermore, tosimplify the operation and implementation of the AD converter whilemaintaining an appropriate degree of accuracy in tuning frequencies.

[0016] A preferred embodiment of the invention is characterised in thatthe bitnumber conversion device comprises a look up table comprising m*nstorage locations for storing therein an n bit binary signal forcontrolling the n capacitors of the integrated digitally controlledcapacitor bank.

[0017] The bitnumber conversion device may alternatively comprise amicroprocessor for executing an algorithm for converting an m bit binarysignal into an n bit binary signal.

[0018] Preferably, the bitnumber conversion device comprise means foradjusting the dependency of capacitance variation of the integrateddigitally controlled capacitor bank on the control signal e.g. to effectlinear dependency between the tuning frequency and said control signal.

[0019] Another object of the invention is to adapt the control of the ncapacitors of the capacitor bank to the actual spread in capacitorvalues.

[0020] A preferred embodiment of the invention is thereforecharacterised by a calibration circuit for measuring absolute spread inthe capacitance values of the n capacitors of the integrated capacitorbank being coupled to the bitnumber conversion device to adapt saidconversion to compensate for said absolute spread.

[0021] This measure provides for an elimination of the absolute spreadfrom the tuning behaviour of the receiver and in particular the RF inputfilter thereof.

[0022] It is yet another object of the invention to improve receiversignal selection and processing.

[0023] An embodiment of a receiver according to the invention istherefore characterised by an RF input filter comprising a furthercapacitor bank being controlled by a control signal generator comprisingmeans to provide parallel tracking of the tuning circuit and the RFfilter.

[0024] Such means may include various look up tables each comprising m*nstorage locations for storing therein the n bit binary signalcontrolling the n capacitors of the integrated digitally controlledcapacitor bank, or may alternatively include means to execute analgorithm which performs the same task.

[0025] Another object of the invention is to avoid the discrete—or stepwise—capacitance variation of the capacitor bank from becoming criticalin some specific applications thereof. In particular when being appliedin phase locked loops.

[0026] Therefore, a preferred embodiment of a receiver according to theinvention is being characterised by a phase locked loop comprising acontrollable oscillator, a continuous tuning control signal beingsupplied through an analogue to digital (AD) converter to said capacitorbank and to a first input of a differential stage, an output of the ADconverter being coupled through a digital to analogue (DA) converter toa second input of a differential stage, an output of the differentialstage being coupled to a control terminal of a variable capacitancediode being arranged in parallel to the capacitor bank.

[0027] This measure prevents the phase locked loop from repeatedswitching between two settings of the digitally controlled capacitorbank.

[0028] A variable capacitance device according to the invention for usein the last mentioned receiver is characterised by a continuous tuningcontrol signal being supplied through an analogue to digital (AD)converter to a further capacitor bank and to a first input of adifferential stage, an output of the AD converter being coupled througha digital to analogue (DA) converter to a second input of a differentialstage, an output of the differential stage being coupled to a controlterminal of a variable capacitance diode being arranged in parallel tothe digitally controlled capacitor bank.

[0029] By applying these measures according to the invention, operationof the digitally controlled capacitor bank within a control rangerequires a much lower supply voltage than conventional variablecapacitance diodes, whereas the variable capacitance diode included inthe variable capacitance device according to the invention only needs tovary within a range corresponding to only one stepwidth of thecapacitance increments of the digitally controlled capacitor bank.

[0030] Preferably, the capacitance variation range of the variablecapacitance diode is chosen to correspond to the capacitance variationstepwidth of the capacitor bank at an incremental change of the outputsignal of the AD converter.

[0031] In a preferred embodiment of the invention, amplification meansare used to adapt the difference between the original analogue controlsignal on the one hand and the digitised analogue control signal for thecapacitor bank on the other hand to the available capacitance controlrange of the variable capacitance diode.

[0032] A further preferred embodiment of the invention allowing linearcontrol of the variable capacitance diode within its capacitancevariation range is characterised by the continuous control signal beingsupplied through said control input to a gain control input of theamplification means.

[0033] Another preferred embodiment of a variable capacitance deviceaccording to the invention, in which the effect of spread is furtherminimised, is characterised by including in a common housing first andsecond look up tables a common input thereof being supplied with atuning control signal and outputs thereof being coupled to first andsecond monolithically integrated digitally controlled capacitor banksfor the use thereof in first and second filter circuits, respectively,the first and second look up tables providing for parallel filtertracking.

[0034] The foregoing and other objects and advantages of the presentinvention will become more readily apparent from the followingdescription of preferred embodiments, as taken in conjunction with theaccompanying drawings, which are a part hereof and wherein:

[0035]FIG. 1A is a functional diagram of a monolithically integrateddigitally controlled capacitor bank according to the invention;

[0036]FIG. 1B is a block diagram of a first preferred embodiment of avariable capacitance device according to the invention as part of an LCcircuit;

[0037]FIG. 2 is a block diagram of a first preferred embodiment of areceiver according to the invention ;

[0038]FIG. 3 is an IC lay out structure used in the implementation ofthe monolithically integrated digitally controlled capacitor bank ofFIG. 1A;

[0039]FIG. 4 is a block diagram of the front end of a second preferredembodiment of a receiver according to the invention using a PLL;

[0040]FIG. 5 is a signal plot showing the capacitance variation within acontrol range of an ideal capacitor bank having 2³=8 discretecapacitance value settings using 3 capacitors without spread;

[0041]FIG. 6 is a signal plot showing the capacitance variation within acontrol range of a monolithically integrated digitally controlledcapacitor bank having 2³=8 discrete capacitance value settings usingfirst to third capacitors, the second capacitor having 30% spread;

[0042]FIG. 7 a block diagram of a second preferred embodiment of avariable capacitance device according to the invention for use intracked filters;

[0043]FIG. 8 a signal plot showing the capacitance versus voltagecharacteristic of a conventional variable capacitance diode.

[0044]FIG. 1A shows a functional diagram of a monolithically integrateddigitally controlled capacitor bank capacitor bank Cb according to theinvention comprising n=10 capacitors C0-C9 forming a binary weightedsequence of values 2⁰ to 2⁹, which can be individually switched throughrespective switches S0-S9 between first and second terminals t1 and t2under control of a digital 10 bit word. A trimmer capacitor Ct isconnected in parallel to the capacitors C0-C9 between the first andsecond terminals t1 and t2. The trimmer capacitor Ct is to compensatefor the unpredictable parasitic capacitances (inherent to the ICimplementation and e.g. caused by bondings) and to bring the totalcapacitance occurring across the capacitor bank to a predetermined fixedvalue Cfix. In practice this fixed value Cfix is kept as small aspossible. An inductor L is coupled in parallel between said first andsecond terminals t1 and t2 to form with the capacitors C0-C9 an LCtuning circuit being controlled in its tuning frequency over a certainfrequency range, for example the AM radio broadcast frequency bandranging from 500 to 1500 Khz. Although in this example, 10 bits areactually required to cover the full tuning frequency range, the relativespread in component values of the capacitors C0-C9 cause the number ofessential information carrying bits to be limited to at most 7 bitsonly. The accuracy in capacitance value obtainable with 7 bits amountsto approximately 1%, which more or less conforms to the accuracyobtainable in an integrated implementation. For small capacitance valuesthe three most significant bits are always zero, i.e. switches S7-S9 arealways open, whereas for large capacitance values the three leastsignificant bits are always irrelevant as their value is less than said1% spread. A 7 bits word can be used according to the invention to varythe capacitance of a capacitor bank with 10 capacitors within a receivertuning range, by applying bit number conversion means to convert said 7bits tuning control signal into a 10 bits tuning control signal for thecapacitor bank. This allows to use a 7 bits AD converter for an analogueto digital conversion of a continuous tuning control signal.

[0045] The bit conversion can be carried out dynamically by using atrial and error calculation scheme. The bit conversion can alternativelybe read out from a look up table in the given example using 10 bits readonly memories addressed by the 7 bit words of the digital tuning controlvoltage. In addition to bit number conversion the look up table may alsocomprise data to provide for compensation of or for adjusting thedependency of capacitance variation of the digitally controlledcapacitor bank on the tuning control signal to effect a lineardependency of the tuning frequency of the LC tuning circuit on saidtuning control signal.

[0046] The function of such look up table will be explained in moredetail with reference to FIG. 7.

[0047]FIG. 1B is a block diagram of a preferred embodiment of a variablecapacitance device Cv according to the invention for use in a receiverin which elements corresponding to the elements shown in FIG. 1A areprovided with same reference numerals. The variable capacitance deviceCv comprises a capacitor bank Cb coupled between first and secondterminals t1 and t2 and connected in parallel to an inductor L to forman LC tuning circuit. The variable capacitance device Cv comprises acontrol input I being supplied with a continuous control signal to varythe capacitance of Cv and therewith the tuning frequency of the LCtuning circuit, this control signal hereinafter also being referred toas tuning control signal Vtune. The control input I is coupled throughan analogue to digital converter AD to a control input of. a digitallycontrolled capacitor bank Cb as well as to a first input of adifferential stage DS. An output of the analogue to digital converter ADis coupled through a digital to analogue converter DA to a second inputof the differential stage DS. An output of the differential stage DS iscoupled through amplification means AMP to a control terminal td of avariable capacitance diode D at the common connection between a serialarrangement of said variable capacitance diode D and a blockingcapacitor C. This serial arrangement is coupled in parallel to thecapacitor bank Cb between said between first and second terminals t1 andt2. The amplification means AMP amplifies the output signal of thedifferential stage DS, i.e. the mutual difference of the signals at thefirst and second input of said differential stage DS—hereinafter alsobeing referred to as discretion difference—to adapt the same to theavailable capacitance variation range of the variable capacitance diodeD. Furthermore by varying the gain of the amplification means AMPdependent on the tuning control voltage Vtune, a compensation of thenon-linear tuning control voltage dependent capacitance variation of thediode D is obtained. As can be seen from the capacitance versus voltagecharacteristic of a conventional variable capacitance diode as shown inFIG. 8, the slope of said characteristic decreases strongly with anincreasing tuning control voltage. By increasing the above gain of theamplification means AMP with an increasing tuning control voltage, thecontrol of the capacitance of the diode D can be made more lineartherewith increasing the control accuracy.

[0048] To provide a continuously varying capacitance value at a likewisevarying tuning control voltage Vtune at the input I, the capacitancevariation range of the variable capacitance diode D should at leastcorrespond to the capacitance variation stepwidth of the capacitor bankCb at an incremental change of the output signal of the AD converter.The capacitance variation range of the variable capacitance diode D ischosen in such a way that it covers safely, even in situations with theworst case process spread, the incremental capacitance variationstepwidth of the capacitor bank. However, to prevent the occurrence ofglitching of the capacitance value of the capacitor bank when beingvaried, the capacitance variation range of the variable capacitancediode D is preferably chosen to be somewhat smaller, in practiseapproximately 10%) of the incremental capacitance variation stepwidth ofthe capacitor bank.

[0049] The variable capacitance device Cv according to the invention asa whole is very well suitable to be substituted for any singleconventional variable capacitance diode and functions properly at supplyvoltages substantially lower than the supply voltage needed for suchconventional variable capacitance diodes. This eliminates the need forDC-DC voltage converters in receivers with low bias voltage. In theabsence of requirements to provide a continuously varying capacitancevalue at a likewise varying tuning control voltage, the use of a singlecapacitor bank, such as the capacitor bank Cb, as substitute for aconventional variable capacitance diode, may suffice. The variablecapacitance device Cv according to the invention, however, fully meetssaid requirements, and its field of use includes all types of tuneablefilters, whether or not being part of a tuning circuit and/or loopcircuit, such as e.g. phase or frequency locked loops.

[0050] The capacitance variation of the variable capacitance device Cvaccording to the invention as shown in FIG. 1B including an idealcapacitor bank with n=3 is given in FIG. 5. Such ideal capacitor bankincludes 3 capacitors without spread and has 2³=8 discrete capacitancesettings. The capacitance variation range of the diode D is chosen tocorrespond to the capacitance variation stepwidth of the capacitor bankat an incremental change of the output signal of the AD converter. Curvecb of FIG. 5 shows the capacitance of the ideal capacitor bank Cb,whereas curve cv of this FIG. 5 is showing the total capacitance of thevariable capacitance device Cv. For each value of the tuning controlinput signal, the variable capacitance device Cv having an idealcapacitor bank Cb defines a certain capacitance value.

[0051] The capacitance variation of a variable capacitance device Cvaccording to the invention as shown in FIG. 1B in a practicalimplementation in integrated form, including a non-ideal capacitor bankwith n=3 is given in FIG. 6. This non-ideal capacitor bank has 2³=8discrete capacitance settings and includes first to third capacitorsC1-C3, in which C2=1.3*C1*2 and in which C3=4*C1. C2 shows a valuespread of 30%. The capacitance variation range of the diode D is chosento cover the capacitance variation stepwidth of the capacitor bank at anincremental change of the output signal of the AD converter. Thecapacitance variation range of the diode D therewith corresponds to thecapacitance variation stepwidth of the capacitor bank at saidincremental change of the output signal of the AD converter. Curve cb ofthis FIG. 6 shows the capacitance of the non-ideal capacitor bank Cb,whereas curve cv is showing the total capacitance of the variablecapacitance device Cv. Also here the variable capacitance device Cvdefines a capacitance value for each value of the tuning control inputsignal. This allows to use the variable capacitance device Cv accordingto the invention as shown in FIG. 1B in phase locked loops as will beexplained in more detail with reference to FIG. 4.

[0052]FIG. 7 shows a block diagram of a second preferred embodiment of avariable capacitance device according to the invention comprising atuning control signal generator CSG being supplied with a tuning controlsignal. The tuning control signal ca n be a continuous signal, in whichevent the tuning control signal generator CSG includes an analogue todigital converter, or the tuning control signal can be a digital signal,in which event the tuning control signal generator CSG may comprisedigital signal processing means and may eventually be dispensed with.The tuning control signal generator CSG supplies an m-bit digital tuningcontrol voltage to inputs of first and second look up tables LU1 andLU2. These first and second look up tables LU1 and LU2 each comprise m*nstorage locations for storing therein respective first and second n bitbinary signals which are supplied to n capacitors of first and secondcapacitor banks Cb1 and Cb2, n being larger than m. The first and secondcapacitor banks Cb1 and Cb2 are monolithically implemented to reduce theabsolute spread and may be commonly mounted in a single housing. Thefirst and second look up tables include, apart from bit numberconversion data also data providing parallel tracking of filters, inwhich the first and second capacitor banks Cb1 and Cb2 are used astuneable capacitance devices. Dependent on the frequency differencebetween such tracked filters, parallel tracking may require thecapacitance of the first capacitor bank Cb1 to vary at a exactlypredictable (calculable), difference from the capacitance of the secondcapacitor bank Cb2 with a certain variation of the n-bit digital tuningcontrol signal. This capacitance difference is to be taken into accountin the generation of the first and second n-bit digital signals. Theimplementation thereof lies within the normal ability of a personskilled in the art and shall therefore not be described in furtherdetail.

[0053] An application of such a variable capacitance device in a firstpreferred embodiment of a receiver according to the invention is shownin FIG. 2. The receiver shown includes an RF input filter comprising afirst parallel LC circuit L1Cb1, formed by an antenna ANT functioning asan inductor Ll and the above first variable capacitor bank Cb1. The RFinput filter is coupled to a mixer stage M for converting an RF signalbeing selected by the RF input filter RF into an IF signal, which IFsignal is being processed in known manner into audible signal in signalprocessing means P. The mixer stage M is supplied with a localoscillator signal being generated by a tuneable oscillator OSCcomprising a second tuneable LC circuit L2Cb2 comprising an inductor L2in parallel with the above second tuneable capacitor bank Cb2. Thecontrollable capacitor banks Cb1 and Cb2 are being provided with firstand second n-bit digital control signals from respectively said firstand second look up tables LU1 and LU2. The frequency of the localoscillator OSC deviates over the IF frequency from the carrier frequencyof the wanted RF signal. For a correct tuning to a wanted RF signalwithin the receiver tuning range, the second tuneable LC circuit L2Cb2should track the first parallel LC circuit L1Cb1 within the receivertuning range over a constant frequency difference corresponding to theIF frequency. This is achieved with a proper adaptation of the abovefirst and second n-bit digital control signal for the first and secondcapacitor banks Cb1 and Cb2.

[0054]FIG. 4 shows an application of a variable capacitance device Cv asshown in FIG. 1B in an RF input filter and an LC tuning circuit of asecond preferred embodiment of a receiver according to the invention. Incontrast to the receiver of FIG. 2, the receiver shown here comprises aphase locked loop (PLL), which includes the tuneable local oscillatorOSC. An output of the local oscillator OSC is compared with a referencefrequency derived from the oscillation frequency of a crystal oscillatorXO in a phase detector of the PLL. Such PLL functions properly only ifwithin the LC tuning circuit a capacitance value is defined for eachfrequency within the tuning range. The absence of capacitance values,which may occur when using a capacitor bank only without a variablecapacitance diode, may give rise to repeatedly switching of thecapacitor bank between two capacitance settings.

[0055] The, LC RF input filter comprises a first parallel LC circuitL1Cv1, formed by an antenna ANT functioning as an inductor L1 and afirst variable capacitance device Cv1 according to the invention. The RFinput filter is coupled to a. mixer stage M for converting an. RF signalbeing selected by the RF input filter RF into an IF signal, which IFsignal is being processed in known manner into audible signal in signalprocessing means P. The mixer stage M is supplied with a localoscillator signal being generated by a tuneable oscillator OSCcomprising a second tuneable LC circuit L2Cv2 comprising an inductor L2in parallel with a second variable capacitance device Cv2 according tothe invention. The first and second capacitor banks of the first andsecond variable capacitance device Cv1 respectively Cv2 includerespectively first and second look up tables LU1 and LU2 (not shown).The frequency of the local oscillator OSC deviates over the IF frequencyfrom the carrier frequency of the wanted RF signal. For a correct tuningto a wanted RF signal within the receiver tuning range, the secondtuneable LC circuit L2Cv2 should track the first parallel LC circuitL1Cv1 within the receiver tuning range over a constant frequencydifference corresponding to the IF frequency. This is achieved with. a.proper adaptation. of the above first and second n-bit digital controlsignal for the first and second capacitor banks Cb1 and Cb2 of the firstand second variable capacitance device Cv1 and Cv2 according to theinvention.

[0056]FIG. 3 shows an IC lay out structure used in the implementation ofthe monolithically integrated digitally controlled capacitor bank ofFIG. 1A and FIG. 1B with n capacitors forming a binary weighted sequenceof values. The integrated n capacitors may be based on the use of oxydelayers or p-n junctions, both technologies being understood to beplanary. The blocks indicated by numbers each represent a unitycapacitor covering a unity IC surface. Among the n capacitors is a unitycapacitor being indicated by a single block, identified with thereference numeral 1 and covering a single unity IC surface. Capacitorssmaller than said unity capacitor 1 are being indicated by blocks A, Band C. These capacitors cover respective IC surfaces, which inproportion to their value are smaller than said unity IC surface,hereinafter also indicated as scaled capacitors. The capacitors greaterthan said unity capacitor are being formed by clusters of a binaryweighted number of unity capacitors referred to by blocks with referencenumerals: 2, 4, 8, 16, 32 and 64. The unity capacitors of the clustersare being surrounded by isolated dummy unity capacitors to provide for acompensation in the lack of neighbouring capacitors on the outerboundaries of the respective clusters, therewith obtaining a furtherminimisation in the relative spread of the various capacitors.Furthermore, the clusters are structured in lay out to minimiseparasitic wiring effects.

[0057] In a practical embodiment the total spread in the capacitancevalue of the unity capacitor is 1%. Therewith all capacitors larger thanthe unity capacitor have a total spread in their capacitance value of1%. Capacitors smaller than the unity capacitor, i.e. capacitors A-C,show a much larger procentual spread in their capacitance value,however, these capacitors are only used in combination with the unitycapacitor and/or one or more capacitors larger than the unity capacitor.This minimises the effect of the larger spread in the capacitance valueof said capacitors A-C on the overall capacitance of the capacitor bankat each value within the control or tuning range.

[0058] Preferably, the n capacitors of the capacitor bank are chosen toform a binary weighted sequence of capacitance values ranging from 2⁰ to2^(n−1), whereas said unity capacitor is chosen to correspond to acapacitance value 2^(k), k being larger than 1 and smaller than n. In apractical embodiment, in which n was in the order of magnitude of 10, anappropriate low spread in the capacitance value of the capacitor bankwithin its control range is obtained with k being chosen in a rangebetween 3 and 8.

[0059] The value of the unity capacitor may also be chosen to definetogether with the above Cfix the upper boundary limit of the tuningrange.

[0060] The smallest capacitor C in the capacitor bank Cb of FIG. 3 ischosen to define the tuning stepwidth. In a practical embodiment theunity capacitor is chosen at a capacitance value of 13.6 pF and thesmallest capacitor C of the capacitor bank at a capacitance value of 1.7pF, While the present invention has been illustrated and described withrespect to some specific embodiments thereof, it is to be understoodthat the present invention is by no means limited thereto, butencompasses all changes and modifications which will become possiblewithin the scope of the appended claims. It is therefore possible toalso use the invention when applying the various measures according tothe invention separately and mutually independent from each other. Forexample, it is very well possible to apply the measure to use of scaledcapacitors in combination with clusters of unity capacitors, the measureto use a bitnumber conversion device and the measure to apply a variablecapacitance diode in parallel to a capacitor bank separately or in anymutual combination, other than shown in the drawing.

1. Receiver comprising a tuning circuit including a digitally controlledcapacitor bank with n capacitors being monolithically integrated inplanary form and being controlled by a tuning control signal,characterised by said n capacitors providing various capacitance valuesincluding a unity capacitor covering a unity IC surface, whereincapacitors having capacitance values smaller than said unity capacitorcover respective IC surfaces, which in proportion to their value aresmaller than said unity IC surface and wherein capacitors havingcapacitance values greater than said unity capacitor are being formed byclusters of capacitors, each covering an IC surface corresponding tosaid unity IC surface.
 2. Receiver according to claim 1, characterisedby said n capacitors forming a binary weighted sequence of capacitancevalues ranging from 2⁰ to 2^(n−1), said unity capacitor corresponding toa capacitance value 2^(k), k being chosen larger than 1 and smaller thann.
 3. Receiver according to claim 2, characterised by n being in theorder of magnitude of 10 and k being chosen in a range between 3 and 8.4. Receiver according to claim 2 or 3, characterised by said unitycapacitor being chosen to define the upper boundary limit of the tuningrange.
 5. Receiver according to one of claims 1 to 4, characterised inthat said clusters of unity capacitors are being surrounded by isolateddummy capacitors.
 6. Receiver according to one of claims 1 to 5,characterised in that the said clusters of capacitors are structured inlay out to minimise parasitic wiring effects.
 7. Receiver according toone of claims 1 to 6, characterised by an AD converter for converting ananalogue tuning control signal into an m bit binary signal being coupledto a bitnumber conversion device for converting said m bit binary signalinto an n bit binary signal, m being smaller than n, said n bit binarysignal including bits 1 to N respectively controlling capacitors 1 to nof the capacitor bank.
 8. Receiver according to claim 7, characterisedin that the bitnumber conversion device comprise means for linearisingthe dependency of capacitance variation of the integrated digitallycontrolled capacitor bank on the tuning control signal.
 9. Receiveraccording to claim 7 or 8, characterised in that the bitnumberconversion device comprises a look up table comprising m*n storagelocations for storing therein the n bit binary signal controlling the ncapacitors of the integrated digitally controlled capacitor bank as afunction of said m bit binary signal.
 10. Receiver according to claim 9,characterised in that the bitnumber conversion device comprises variouslook up tables each comprising m*n storage locations for storing thereinthe n bit binary signal controlling the n capacitors of the integrateddigitally controlled capacitor bank.
 11. Receiver according to claim 7or 8, characterised in that the bitnumber conversion device comprises amicroprocessor for executing an algorithm for converting an m bit binarysignal into an n bit binary signal.
 12. Receiver according to one ofclaims 7 to 11, characterised by a calibration circuit for measuringabsolute spread in the capacitance values of the n capacitors of theintegrated digitally controlled capacitor bank being coupled to thebitnumber conversion device to adapt said conversion to compensate forsaid absolute spread.
 13. Receiver according to one of claims 1 to 12,characterised by a phase locked loop comprising a controllableoscillator, a continuous tuning control signal being supplied through ananalogue to digital (AD) converter to said capacitor bank and to a firstinput of a differential stage, an output of the AD converter beingcoupled through a digital to analogue (DA) converter to a second inputof a differential stage, an output of the differential stage beingcoupled to a control terminal of a variable capacitance diode beingarranged in parallel to the capacitor bank.
 14. Receiver according toclaim 13, characterised in that the capacitance variation range of thevariable capacitance diode corresponds at least to the capacitancevariation stepwidth of the capacitor bank at an incremental change ofthe output signal of the AD converter.
 15. Receiver according to claim13 or 14, characterised by amplification means preceding the controlterminal of said variable capacitance diode for amplifying the mutualdifference of the signals at the first and second input of thedifferential stage.
 16. Receiver according to claim 15, characterised byan output of the AD converter being coupled to a gain control input ofthe amplification means.
 17. Receiver according to one of claims 1 to16, characterised by an RF input filter comprising a further capacitorbank being controlled by a control signal generator comprising means toprovide parallel tracking of the tuning circuit and the RF filter. 18.Variable capacitance device comprising a digitally controlled capacitorbank with n capacitors being monolithically integrated in planary formand being controlled by a control signal for varying the capacitance ofthe capacitor bank, characterised by said n capacitors providing variouscapacitance values including a unity capacitor covering a unity ICsurface, wherein capacitors having capacitance values smaller than saidunity capacitor cover respective IC surfaces, which in proportion totheir value are smaller than said unity IC surface and whereincapacitors having capacitance values greater than said unity capacitorare being formed by clusters of capacitors, each covering an IC surfacecorresponding to said unity IC surface.
 19. Variable capacitance deviceaccording to claim 18, characterised by said n capacitors forming abinary weighted sequence of capacitance values ranging from 2⁰ to2^(n−1), said unity capacitor corresponding to a capacitance value2^(k), k being chosen larger than 1 and smaller than n.
 20. Variablecapacitance device according to claim 19, characterised by n being inthe order of magnitude of 10 and k being chosen in a range between 3 and8.
 21. Variable capacitance device according to claim 19 or 20,characterised by said unity capacitor being chosen to define the upperboundary limit of the control range.
 22. Variable capacitance deviceaccording to one of claims 18 to 21, characterised in that said clustersof unity capacitors are being surrounded by isolated dummy capacitors.23. Variable capacitance device according to one of claims 18 to 22,characterised in that the said clusters of capacitors are structured inlay out to minimise parasitic wiring effects.
 24. Variable capacitancedevice according to one of claims 18 to 23 characterised by an ADconverter for converting an analogue control signal into an m bit binarysignal being coupled to a bitnumber conversion device for convertingsaid m bit binary signal into an n bit binary signal, m being smallerthan n, said n bit binary signal including bits 1 to N respectivelycontrolling capacitors 1 to n of the capacitor bank.
 25. Variablecapacitance device according to claim 24, characterised in that thebitnumber conversion device comprise means for linearising thedependency of capacitance variation of the integrated digitallycontrolled capacitor bank on the control signal.
 26. Variablecapacitance device according to claim 24 or 25, characterised in thatthe bitnumber conversion device comprises a look up table comprising m*nstorage locations for storing therein the n bit binary signalcontrolling the n capacitors of the integrated digitally controlledcapacitor bank as a function of said m bit binary signal.
 27. Variablecapacitance device according to claim 26, characterised in that thebitnumber conversion device comprises various look up tables eachcomprising m*n storage locations for storing therein the n bit binarysignal controlling the n capacitors of the integrated digitallycontrolled capacitor bank.
 28. Variable capacitance device according toclaim 24 or 25, characterised in that the bitnumber conversion devicecomprises a microprocessor for executing an algorithm for converting anm bit binary signal into an n bit binary signal.
 29. Variablecapacitance device according to one of claims 18 to 30, characterised bya phase locked loop comprising a controllable oscillator, a continuouscontrol signal being supplied through an analogue to digital (AD)converter to said capacitor bank and to a first input of a differentialstage, an output of the AD converter being coupled through a digital toanalogue (DA) converter to a second input of a differential stage, anoutput of the differential stage being coupled to a control terminal ofa variable capacitance diode being arranged in parallel to the capacitorbank.
 30. Variable capacitance device according to claim 29,characterised in that the capacitance variation range of the variablecapacitance diode corresponds at least to the capacitance variationstepwidth of the capacitor bank at an incremental change of the outputsignal of the AD converter.
 31. Variable capacitance device according toclaim 29 or 30, characterised by amplification means preceding thecontrol terminal of said variable capacitance diode for amplifying themutual difference of the signals at the first and second input of thedifferential stage.
 32. Variable capacitance device according to claim31, characterised by an output of the AD converter being coupled to again control input of the amplification means.
 33. Variable capacitancedevice according to one of claims 24 to 32, characterised by acalibration circuit for measuring absolute spread in the capacitancevalues of the n capacitors of the integrated digitally controlledcapacitor bank being coupled to the bitnumber conversion device to adaptsaid conversion to compensate for said absolute spread.
 34. Variablecapacitance device according to one of claims 27 to 33, characterised byincluding in a common housing first and second look up tables a commoninput thereof being supplied with a control signal and outputs thereofbeing coupled to first and second monolithically integrated digitallycontrolled capacitor banks for the use thereof in first and secondfilter circuits, respectively, the first and second look up tablesproviding for parallel filter tracking.